Low Power Heterogeneous Adder

Flexibility and Portability has increased the requirement of Low Power components in fields like multimedia, signal processing and other computing applications. Adders are the essential computing elements in such applications. However the present adder architectures with hybrid/heterogeneous features provide performance variations but limits to consume less power. In this paper, low power heterogeneous adder architecture is proposed to enable flexibility to the computing applications and consume less power. 128 bit heterogeneous adder architecture is built using three low power sub-adders (ripple carry, carry look ahead and carry bypass adders). Adder variants in sub-adders block of heterogeneous adder architecture enables to select required quality metrics viz., area, timing and power, for the design. Application requirements like low power – same performance, low power – low area, variable performance can be selected. Designs are demonstrated using Verilog HDL by synthesizing with Cadence’s RTL Compiler and mapped to TSMC 65nm technological library node. Key-Words: Heterogeneous adder, Power delay trade-off, Low Power VLSI, Digital Filter, Verilog